The present invention relates to a nonvolatile semiconductor memory device and its manufacturing method, and more particularly to techniques of realizing high integration and reliability of a nonvolatile semiconductor memory device capable of electrical programming.
Of electrically programmable nonvolatile semiconductor memory devices, a bulk erasable memory or so-called flash memory is known. Flash memories provide excellent portability and shock resistance and are electrically bulk erasable. For these reasons, demands for flash memories as storage devices of compact portable information apparatuses such as portable personal computers and digital still cameras are rapidly increasing. Reduction in a bit cost by a smaller memory cell area is an important factor for market expansion. Various memory cells realizing this have been proposed, for example, as described in “Ohyo Butsuri (or Applied Physics)”, Vol. 65, No. 11, pp. 1114–1124 published by the Japan Society of Applied Physics on Nov. 10, 1996 (hereinafter called “Document 1”).
A virtual ground type memory cell utilizing a three-layer polysilicon gate is described, for example, in JP-B-2694618 (registered on Sep. 12, 1997) corresponding to U.S. Pat. No. 5,095,344. This memory cell is constituted of semiconductor regions formed in a well of a semiconductor substrate and three gates. The three gates include a control gate formed on the well and an erase gate formed between the control gate and a floating gate disposed near each other. These three gates are made of polysilicon and are separated by insulator films. The floating gate and well are also separated by an insulator film. The control gate extending in the row direction constitutes a word line. The source/drain diffusion regions are formed along the column direction and are of a virtual ground type that shares the diffusion regions with adjacent memory cells. With this layout, a pitch in the row direction can be reduced. The erase gate is parallel to the channel and disposed between and in parallel to the word lines (control gates). In writing data in a memory cell described in Document 1, independent positive voltages are applied to the word line and drain, and 0 V is applied to the well, source and erase gate. Hot electrons are therefore generated in the channel region near the drain so that electrons are injected into the floating gate and the threshold voltage of the memory cell rises. In erasing data in the memory cell, a positive voltage is applied to the erase gate, and 0 V is applied to the word line, source, drain and well. Electrons are drained from the floating gate into the erase gate so that the threshold voltage lowers.
A split-gate type memory cell is disclosed, for example, in JP-A-9-321157 (laid open on Dec. 12, 1997). In this memory cell, a large overlap is formed between a diffusion layer and a floating gate to raise the floating gate potential by the diffusion layer potential and apply a low voltage to the word line. In this manner, the efficiency of generating and injecting hot electrons during data write can be improved.
A method of controlling the floating gate potential by the word line and controlling the split channel by a third gate different from the floating and control gates is discussed, for example, in the “Technical Digest” at the International Electron Devices Meeting, 1989, pp. 603–606.